)]}' { "log": [ { "commit": "510355478850fb9bb4b064554d3dc2416b8b4b96", "tree": "ac3d3df9f039e1aaa8e9e2833c271e7458289a16", "parents": [ "e3ce71f05b4ddf272bb7ab39a0154acf83ef3f9c", "1c525bbe1c5e8477bc78d3b3be812d94074cb5bc" ], "author": { "name": "Yann Gautier", "email": "yann.gautier@st.com", "time": "Mon Oct 05 12:25:34 2026" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Mon Oct 05 12:25:34 2026" }, "message": "Merge \"fix(tsp): use VERBOSE instead of INFO\" into integration" }, { "commit": "1c525bbe1c5e8477bc78d3b3be812d94074cb5bc", "tree": "ac3d3df9f039e1aaa8e9e2833c271e7458289a16", "parents": [ "e3ce71f05b4ddf272bb7ab39a0154acf83ef3f9c" ], "author": { "name": "Boyan Karatotev", "email": "boyan.karatotev@arm.com", "time": "Mon Sep 21 09:40:42 2026" }, "committer": { "name": "Boyan Karatotev", "email": "boyan.karatotev@arm.com", "time": "Mon Oct 05 10:22:10 2026" }, "message": "fix(tsp): use VERBOSE instead of INFO\n\nThe tsp is quite vocal about what it does, however on regular DEBUG\nbuilds this drowns out everything else. Switch the INFO statements to\nVERBOSE to help combat this. tsp-ffa already does this.\n\nChange-Id: I078f3209dc1b788f8341fbab64e8149147101aea\nSigned-off-by: Boyan Karatotev \u003cboyan.karatotev@arm.com\u003e\n" }, { "commit": "e3ce71f05b4ddf272bb7ab39a0154acf83ef3f9c", "tree": "534e9e66118bf3ba2a00ead15188eb603b10415b", "parents": [ "3d425f4f459820a44d24b23464dbc09d6baab7bb", "9584865f1de741d99b43c3ad49b1969df69a6d14" ], "author": { "name": "Harrison Mutai", "email": "harrison.mutai@arm.com", "time": "Mon Oct 05 08:14:09 2026" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Mon Oct 05 08:14:09 2026" }, "message": "Merge \"docs(build): update GCC toolchain requirement to 15.3.Rel1\" into integration" }, { "commit": "3d425f4f459820a44d24b23464dbc09d6baab7bb", "tree": "2cffd1837ec18a6ec2ccecc41a8eba97d7abcfc6", "parents": [ "574a70e0f405ff2321118bf691ae3003c4af6750", "707740c5999edfe7401483cf4fc157c7de70f1ea" ], "author": { "name": "Manish V Badarkhe", "email": "manish.badarkhe@arm.com", "time": "Fri Oct 02 07:59:33 2026" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Fri Oct 02 07:59:33 2026" }, "message": "Merge changes Ic3cde7b7,Ic8c997ea,Ica071fcd,Ic0a2ae68,Ib5194ac1, ... into integration\n\n* changes:\n feat(st): allow booting Linux directly\n feat(st): use x0 for physical address of device tree blob\n refactor(stm32mp2): print reset reason at a lower log level\n refactor(stm32mp1): print reset reason at a lower log level\n feat(stm32mp2): enable LTO support in STM32MP2\n feat(stm32mp2): boot BL33 at EL2 by default\n fix(stm32mp25-fdts): align rcc node with Linux\n" }, { "commit": "574a70e0f405ff2321118bf691ae3003c4af6750", "tree": "35b030e0e7654c7219008756969205563c25df12", "parents": [ "634d24110e2a9ac7ffd1aee72dc394ba46639fc7", "d1f4fb2579cf5a940e37d6b597ef298da38743af" ], "author": { "name": "Boyan Karatotev", "email": "boyan.karatotev@arm.com", "time": "Thu Oct 01 19:30:38 2026" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Thu Oct 01 19:30:38 2026" }, "message": "Merge \"fix(cpufeat): use PMECR_EL1 register encoding\" into integration" }, { "commit": "d1f4fb2579cf5a940e37d6b597ef298da38743af", "tree": "35b030e0e7654c7219008756969205563c25df12", "parents": [ "634d24110e2a9ac7ffd1aee72dc394ba46639fc7" ], "author": { "name": "Gabor Balogh", "email": "gabor.balogh@arm.com", "time": "Thu Oct 01 13:00:25 2026" }, "committer": { "name": "Gabor Balogh", "email": "gabor.balogh@arm.com", "time": "Thu Oct 01 15:45:02 2026" }, "message": "fix(cpufeat): use PMECR_EL1 register encoding\n\nDefinition added to support of older assemblers.\n\nChange-Id: Id47bd0834e048b435f66c28ba30f9f516b05588e\nSigned-off-by: Gabor Balogh \u003cgabor.balogh@arm.com\u003e\n" }, { "commit": "707740c5999edfe7401483cf4fc157c7de70f1ea", "tree": "7121059d0975ed5e745826ae4714a22e9eb08027", "parents": [ "b32de86e05df2f589471fc1654f457fdcd63db5f" ], "author": { "name": "Yann Gautier", "email": "yann.gautier@st.com", "time": "Tue Jun 11 08:50:32 2024" }, "committer": { "name": "Yann Gautier", "email": "yann.gautier@st.com", "time": "Thu Oct 01 15:12:03 2026" }, "message": "feat(st): allow booting Linux directly\n\nManage the flag ARM_LINUX_KERNEL_AS_BL33 in ST common.mk file.\nFor STM32MP1x, put Linux at the beggining of DDR + 0x8000, and with\nmax size set to 0x5FF8000.\nFor STM32MP2x, just increase the max allocated size for BL33 to 128MB.\n\nChange-Id: Ic3cde7b7ab759732d4cfe8b1a9db0196f8e4c7ba\nSigned-off-by: Yann Gautier \u003cyann.gautier@st.com\u003e\n" }, { "commit": "b32de86e05df2f589471fc1654f457fdcd63db5f", "tree": "a9bcfa6e412232c0a12eea9fdd49952cbfb3ebfe", "parents": [ "90fe616c8cc8428ecdb4beb864949921b5c32912" ], "author": { "name": "Maxime Méré", "email": "maxime.mere@foss.st.com", "time": "Thu Mar 27 09:56:38 2025" }, "committer": { "name": "Yann Gautier", "email": "yann.gautier@st.com", "time": "Thu Oct 01 15:12:03 2026" }, "message": "feat(st): use x0 for physical address of device tree blob\n\nUse BL33 parameter x0 for physical address of device tree blob (dtb) in\nsystem RAM as expected by Linux kernel.\nThis change is also managed in U-Boot since v2025.10.\n\nChange-Id: Ic8c997ea59ed299594cb4eb27db546b4e68a783a\nSigned-off-by: Maxime Méré \u003cmaxime.mere@foss.st.com\u003e\n" }, { "commit": "90fe616c8cc8428ecdb4beb864949921b5c32912", "tree": "d068c9c4e683c21f3b024b137c4debc3a6b459e0", "parents": [ "e1d4eaf8d46cb03fcdde02345da2d56dc9ef197b" ], "author": { "name": "Maxime Méré", "email": "maxime.mere@foss.st.com", "time": "Fri Dec 12 14:08:49 2025" }, "committer": { "name": "Yann Gautier", "email": "yann.gautier@st.com", "time": "Thu Oct 01 15:12:03 2026" }, "message": "refactor(stm32mp2): print reset reason at a lower log level\n\nThe reset reason is important information that should be printed even at\nthe NOTICE log level.\n\nChange-Id: Ica071fcd92c6a0bf51d743bc7ac14ffaa9e6d998\nSigned-off-by: Maxime Méré \u003cmaxime.mere@foss.st.com\u003e\n" }, { "commit": "e1d4eaf8d46cb03fcdde02345da2d56dc9ef197b", "tree": "278b93ac6bbeb3d38fe17d9497a58b6eeb86b79f", "parents": [ "50794ea423baeff748ba9b6a09e5375722fa682b" ], "author": { "name": "Maxime Méré", "email": "maxime.mere@foss.st.com", "time": "Fri Dec 12 14:08:33 2025" }, "committer": { "name": "Yann Gautier", "email": "yann.gautier@st.com", "time": "Thu Oct 01 15:12:03 2026" }, "message": "refactor(stm32mp1): print reset reason at a lower log level\n\nThe reset reason is important information that should be printed even at\nthe NOTICE log level.\n\nChange-Id: Ic0a2ae68d21c7f63932a28fe390cf98f18dc776c\nSigned-off-by: Maxime Méré \u003cmaxime.mere@foss.st.com\u003e\n" }, { "commit": "50794ea423baeff748ba9b6a09e5375722fa682b", "tree": "67899610a51c9234fe619f43642d8acfc05841f8", "parents": [ "d5d413d1929318fdef1aabcdbcca4c5ca9163d8c" ], "author": { "name": "Maxime Méré", "email": "maxime.mere@foss.st.com", "time": "Fri Dec 13 13:12:32 2024" }, "committer": { "name": "Yann Gautier", "email": "yann.gautier@st.com", "time": "Thu Oct 01 15:12:03 2026" }, "message": "feat(stm32mp2): enable LTO support in STM32MP2\n\nAllow the usage of link time optimization in STM32MP2 platform and\nenable it. When enabled, PIE must be disabled as bl2 and bl31 base\naddress must be absolute otherwise some ASM function will fail.\n\nChange-Id: Ib5194ac10501e20c06dc646c1f6e2e24039c0637\nSigned-off-by: Maxime Méré \u003cmaxime.mere@foss.st.com\u003e\n" }, { "commit": "d5d413d1929318fdef1aabcdbcca4c5ca9163d8c", "tree": "1540b0841c9d3c38798b0592b95876cd6ab02709", "parents": [ "dced5ba857d78d2932260dd1a5de68074c1f324e" ], "author": { "name": "Maxime Méré", "email": "maxime.mere@foss.st.com", "time": "Fri Nov 22 13:36:19 2024" }, "committer": { "name": "Yann Gautier", "email": "yann.gautier@st.com", "time": "Thu Oct 01 15:12:03 2026" }, "message": "feat(stm32mp2): boot BL33 at EL2 by default\n\nSet BL33 to boot at EL2 by default. The STM32MP_BL33_EL1 must be\nmanually enabled to boot at EL1.\nWhile at it, document the flag in STM32MP2 documentation.\n\nChange-Id: I9c5a183553c5b2f54c55877ecb7b02e04cb333e6\nSigned-off-by: Maxime Méré \u003cmaxime.mere@foss.st.com\u003e\n" }, { "commit": "dced5ba857d78d2932260dd1a5de68074c1f324e", "tree": "b2a294213ffcccadc4d28ec55727125a3336376a", "parents": [ "634d24110e2a9ac7ffd1aee72dc394ba46639fc7" ], "author": { "name": "Patrick Delaunay", "email": "patrick.delaunay@foss.st.com", "time": "Tue Jul 30 13:32:44 2024" }, "committer": { "name": "Yann Gautier", "email": "yann.gautier@st.com", "time": "Thu Oct 01 15:12:03 2026" }, "message": "fix(stm32mp25-fdts): align rcc node with Linux\n\nAlignment with linux kernel device tree, use the correct binding.\n\nSigned-off-by: Patrick Delaunay \u003cpatrick.delaunay@foss.st.com\u003e\nChange-Id: Ib3dc18dac2b3b4b8111cbd57021298ec8a250ee1\n" }, { "commit": "634d24110e2a9ac7ffd1aee72dc394ba46639fc7", "tree": "7f47419d8c76a652aa76d50319d5666e1605de15", "parents": [ "eed1f67cc600a7dac84076b6315fb71734b07ca7", "e0f306872e958ee25565f126d13fe7d0828644ee" ], "author": { "name": "Harrison Mutai", "email": "harrison.mutai@arm.com", "time": "Thu Oct 01 10:39:49 2026" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Thu Oct 01 10:39:49 2026" }, "message": "Merge \"fix(cert-create): generate only keys needed by requested certificates\" into integration" }, { "commit": "9584865f1de741d99b43c3ad49b1969df69a6d14", "tree": "576e6dad87574dfa4884c06ee7697a5484699413", "parents": [ "58bd918dce1e2831fbec252c0b2139d519a00d55" ], "author": { "name": "Jayanth Dodderi Chidanand", "email": "jayanthdodderi.chidanand@arm.com", "time": "Thu Sep 03 18:03:20 2026" }, "committer": { "name": "Jayanth Dodderi Chidanand", "email": "jayanthdodderi.chidanand@arm.com", "time": "Thu Oct 01 10:19:55 2026" }, "message": "docs(build): update GCC toolchain requirement to 15.3.Rel1\n\nUpdate documentation to reflect the use of GCC version 15.3.Rel1,\nthe latest production release available at:\nhttps://developer.arm.com/downloads/-/arm-gnu-toolchain-downloads\n\nSigned-off-by: Jayanth Dodderi Chidanand \u003cjayanthdodderi.chidanand@arm.com\u003e\nChange-Id: If4c074c3089a076fd23e80e2317e90fb1afae8d3\n" }, { "commit": "eed1f67cc600a7dac84076b6315fb71734b07ca7", "tree": "de2948cbf430a704750cd69e27f2c5e59bd3791e", "parents": [ "ef1f53b31d065a0fd32ceec3a9250ba479a613a0", "4a133a5678ceab104f3f51f2e451635999e5366b" ], "author": { "name": "Boyan Karatotev", "email": "boyan.karatotev@arm.com", "time": "Thu Oct 01 09:43:40 2026" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Thu Oct 01 09:43:40 2026" }, "message": "Merge changes from topic \"st_shadow_prov\" into integration\n\n* changes:\n feat(fdts): add default hconf1 OTP value for stm32mp257f-ev\n feat(st): add a provisioning mode to manage shadow OTP\n feat(st): add interface to get otp from phandle\n" }, { "commit": "ef1f53b31d065a0fd32ceec3a9250ba479a613a0", "tree": "2401f4f4cf906965b1e1086119fc114e54b97446", "parents": [ "46430dc82563d8910360cef630d35e6c03d18453", "c5450ae975e489af353c956c60c48ffa23473bae" ], "author": { "name": "Harrison Mutai", "email": "harrison.mutai@arm.com", "time": "Thu Oct 01 09:35:58 2026" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Thu Oct 01 09:35:58 2026" }, "message": "Merge \"fix(qti): correct power driver init sequence\" into integration" }, { "commit": "46430dc82563d8910360cef630d35e6c03d18453", "tree": "8954642f8738373376b58017c26dda56435d5806", "parents": [ "5551a7772fcaab61f547b7a84af7437ed9776e57", "70132f5146b7c3183c9683d3101992dfb38dca0e" ], "author": { "name": "Harrison Mutai", "email": "harrison.mutai@arm.com", "time": "Thu Oct 01 08:59:14 2026" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Thu Oct 01 08:59:14 2026" }, "message": "Merge changes from topic \"lemans_cpucp_start\" into integration\n\n* changes:\n feat(qti): start CPUCP from BL31 on Lemans\n feat(qti): add common hoya CPUCP start infrastructure\n" }, { "commit": "5551a7772fcaab61f547b7a84af7437ed9776e57", "tree": "08666e02a37a2d2306694039c0478a8df64b7a37", "parents": [ "edb4744dbb3a50563d8de8ccf3288b8672369a5e", "540134b53d7892f2383739aad5f0b2a2069134c1" ], "author": { "name": "Manish Pandey", "email": "manish.pandey2@arm.com", "time": "Wed Sep 30 21:44:31 2026" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Wed Sep 30 21:44:31 2026" }, "message": "Merge changes Ib49aae42,I198a8b8c,I979cbe59,Ic60963df into integration\n\n* changes:\n feat(cpufeat): complete branch recording at EL3\n refactor(cpufeat): modularised EL3 sync exceptions\n fix: correct ISS_DFSC_WIDTH\n refactor(rme): panic on non-recoverable exception\n" }, { "commit": "e0f306872e958ee25565f126d13fe7d0828644ee", "tree": "b6e24a054dc4539399b01a186d2f67d83ee6fe81", "parents": [ "19359dc064bcfbc32663a43a1e909c9776f11fa6" ], "author": { "name": "Vikrant Yadav", "email": "vikrantyadav4802@gmail.com", "time": "Tue Sep 29 15:11:15 2026" }, "committer": { "name": "Vikrant Yadav", "email": "vikrantyadav4802@gmail.com", "time": "Wed Sep 30 12:50:05 2026" }, "message": "fix(cert-create): generate only keys needed by requested certificates\n\nDerive the required key set from required certificates, including\ntheir own, issuer signing, and public-key extension keys.\nApply it to validation, key load/create, and key save so a subset\nrequest does not create or require unrelated keys.\n\nTests:\n- Before fix (generated unrequested keys and logs ERROR on missing\n key filenames):\n $ ./cert_create -n -k --tb-fw-cert tb_fw.crt --tb-fw bl2.bin \\\n\t--tfw-nvctr 0 --rot-key rot.key\n NOTICE: Creating new key for \u0027Root Of Trust key\u0027\n NOTICE: Creating new key for \u0027Trusted World key\u0027\n ...\n ERROR: Key filename not specified\n ERROR: Cannot save Trusted World key\n\n- After fix (creates/saves only the required keys for requested cert):\n $ ./cert_create -n -k --tb-fw-cert tb_fw.crt --tb-fw bl2.bin \\\n\t--tfw-nvctr 0 --rot-key rot.key\n NOTICE: Creating new key for \u0027Root Of Trust key\u0027\n NOTICE: Saving key \u0027Root Of Trust key\u0027 to \u0027rot.key\u0027\n NOTICE: Certificate \u0027tb_fw.crt\u0027 generated successfully\n\nChange-Id: I34ab5c3b0e0adbec7b42f7142679ee8389c56d77\nSigned-off-by: Vikrant Yadav \u003cvikrantyadav4802@gmail.com\u003e\n" }, { "commit": "4a133a5678ceab104f3f51f2e451635999e5366b", "tree": "e9261d8282e2dd427d1e7db4cbf4d92c56911952", "parents": [ "38b691adef6d2d59d05a0e777f7d2edb81964811" ], "author": { "name": "Yann Gautier", "email": "yann.gautier@st.com", "time": "Thu Nov 03 16:27:01 2022" }, "committer": { "name": "Yann Gautier", "email": "yann.gautier@st.com", "time": "Wed Sep 30 12:15:32 2026" }, "message": "feat(fdts): add default hconf1 OTP value for stm32mp257f-ev\n\nAdd the default shadow value to allow 1.8V management\non VDDIO1\u00262.\n\nSigned-off-by: Yann Gautier \u003cyann.gautier@st.com\u003e\nChange-Id: I798a36c178fdcc1709785c100f0b0c9793a3a956\n" }, { "commit": "38b691adef6d2d59d05a0e777f7d2edb81964811", "tree": "e0ed2319f30e2f821419552a795a526e27cfebca", "parents": [ "e48b874652fb359d590e42d3c4ec4c1860245b5e" ], "author": { "name": "Lionel Debieve", "email": "lionel.debieve@foss.st.com", "time": "Wed Sep 21 13:22:23 2022" }, "committer": { "name": "Yann Gautier", "email": "yann.gautier@st.com", "time": "Wed Sep 30 12:15:32 2026" }, "message": "feat(st): add a provisioning mode to manage shadow OTP\n\nAdd a provisioning feature based on firmware configuration\nframework that adds in the shadow registers some required\nfunctionality to avoid burning fuses for testing purpose.\n\nSigned-off-by: Lionel Debieve \u003clionel.debieve@foss.st.com\u003e\nChange-Id: I2f5a54fca8692baf008f4c6efbda1d377922e024\n" }, { "commit": "e48b874652fb359d590e42d3c4ec4c1860245b5e", "tree": "11de00881549194ad274f72ee091b706490a2338", "parents": [ "edb4744dbb3a50563d8de8ccf3288b8672369a5e" ], "author": { "name": "Lionel Debieve", "email": "lionel.debieve@foss.st.com", "time": "Mon Sep 19 12:44:37 2022" }, "committer": { "name": "Yann Gautier", "email": "yann.gautier@st.com", "time": "Wed Sep 30 12:15:32 2026" }, "message": "feat(st): add interface to get otp from phandle\n\nAdd an interface to retrieve an OTP (id and size) from\na given phandle.\n\nSigned-off-by: Lionel Debieve \u003clionel.debieve@foss.st.com\u003e\nChange-Id: Ida0550a05e4612b5ae718b3201cab4dc3702c3f9\n" }, { "commit": "edb4744dbb3a50563d8de8ccf3288b8672369a5e", "tree": "e81ac68aea31b051c457e309fc662c2d425586cf", "parents": [ "58bd918dce1e2831fbec252c0b2139d519a00d55", "8e37d1f6be12d35cc1ceab6cf6cb476b8635e5f6" ], "author": { "name": "Boyan Karatotev", "email": "boyan.karatotev@arm.com", "time": "Wed Sep 30 08:46:45 2026" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Wed Sep 30 08:46:45 2026" }, "message": "Merge changes from topic \"st_crypto_updates\" into integration\n\n* changes:\n feat(stm32mp25-fdts): add crypro peripherals\n feat(stm32mp13-fdts): change PKA compatible name\n feat(st-crypto): change PKA compatible name\n feat(st-crypto): add STM32MP21 SAES driver support\n fix(st-crypto): adapt kshareid values for STM32MP25\n feat(st-crypto): check if SAES is already initialized\n fix(st-crypto): use static CLKDIV for RNG on MP2x platforms\n fix(st-crypto): increase RNG robustness for STM32MP21\n feat(st-crypto): improve RNG parameter for all platform\n feat(st-crypto): manage RNG customization with device tree\n refactor(st-crypto): split RNG NIST configuration\n" }, { "commit": "8e37d1f6be12d35cc1ceab6cf6cb476b8635e5f6", "tree": "e81ac68aea31b051c457e309fc662c2d425586cf", "parents": [ "f06166d4b8647009de3d4b263a552bab21f1305a" ], "author": { "name": "Maxime Méré", "email": "maxime.mere@foss.st.com", "time": "Wed Jan 18 12:50:30 2023" }, "committer": { "name": "Yann Gautier", "email": "yann.gautier@st.com", "time": "Tue Sep 29 17:33:11 2026" }, "message": "feat(stm32mp25-fdts): add crypro peripherals\n\nAdd nodes in device tree for CRYP, HASH, PKA and SAES peripherals.\nHASH is available for all STM32MP2 SoCs, so add it in stm32mp251.dtsi.\nCRYP1, CRYP2, PKA and SAES are only available for STM32MP25xC or\nSTM32MP25xF versions.\nAdd the nodes in the corresponding dtsi files.\n\nSigned-off-by: Maxime Méré \u003cmaxime.mere@foss.st.com\u003e\nChange-Id: Ia0f035aa5caad22ae76680a7d610815f952731ef\n" }, { "commit": "f06166d4b8647009de3d4b263a552bab21f1305a", "tree": "5b8cf89aa8772b793ef668e43da106bbd1175667", "parents": [ "48005b8cd3a4e1b8f51ce464b33cf1ecb6ca9751" ], "author": { "name": "Maxime Méré", "email": "maxime.mere@foss.st.com", "time": "Fri Aug 30 12:50:09 2024" }, "committer": { "name": "Yann Gautier", "email": "yann.gautier@st.com", "time": "Tue Sep 29 16:36:05 2026" }, "message": "feat(stm32mp13-fdts): change PKA compatible name\n\nChange PKA compatible name to match other ST device tree.\n\nSigned-off-by: Maxime Méré \u003cmaxime.mere@foss.st.com\u003e\nChange-Id: I5e6f72e68ebc90a114d2310e69d1adfb68da287e\n" }, { "commit": "48005b8cd3a4e1b8f51ce464b33cf1ecb6ca9751", "tree": "6031267978f171962dda57d5939ed28212040f83", "parents": [ "dc0f2afff3fc7f58ced51a93713497ddcbe6b666" ], "author": { "name": "Maxime Méré", "email": "maxime.mere@foss.st.com", "time": "Fri Aug 30 12:48:38 2024" }, "committer": { "name": "Yann Gautier", "email": "yann.gautier@st.com", "time": "Tue Sep 29 16:36:05 2026" }, "message": "feat(st-crypto): change PKA compatible name\n\nChange compatible name of PKA to match other ST device tree\n\nSigned-off-by: Maxime Méré \u003cmaxime.mere@foss.st.com\u003e\nChange-Id: I2176950d06567473a23d313afd85c74d32586d14\n" }, { "commit": "dc0f2afff3fc7f58ced51a93713497ddcbe6b666", "tree": "f47fcab89b3717aade948f382c3e7d35ac924d73", "parents": [ "e2a0c57478295eb2c684fcd02c7abbc4a4d2dc39" ], "author": { "name": "Maxime Méré", "email": "maxime.mere@foss.st.com", "time": "Mon Apr 22 09:15:40 2024" }, "committer": { "name": "Yann Gautier", "email": "yann.gautier@st.com", "time": "Tue Sep 29 16:36:05 2026" }, "message": "feat(st-crypto): add STM32MP21 SAES driver support\n\nThis patch makes this driver compatible with STM32MP21 SoC.\nThis implies bit-field modification and also support of 192 bit key\nsize. Please note that on STM32MP21, the CCF bit from ISR register is\nno more replicated in SR register. Directly read CCF from ISR register.\n\nExplicitly disable STM32_SAES_CRYP2 flag on STM32MP1 platform on which\nthe feature is not supported.\nThis avoids warnings when enabling -Wundef flag.\n\nSigned-off-by: Maxime Méré \u003cmaxime.mere@foss.st.com\u003e\nChange-Id: Ic3a55c68e5052099b001e61adeca25edd887e631\n" }, { "commit": "e2a0c57478295eb2c684fcd02c7abbc4a4d2dc39", "tree": "7be0e9be02631d67773ef9716c3c388bba66e6f4", "parents": [ "7dd90ad0a313c3e00eab4323414d119aaee4a1ce" ], "author": { "name": "Maxime Méré", "email": "maxime.mere@foss.st.com", "time": "Tue Feb 06 13:54:19 2024" }, "committer": { "name": "Yann Gautier", "email": "yann.gautier@st.com", "time": "Tue Sep 29 16:36:05 2026" }, "message": "fix(st-crypto): adapt kshareid values for STM32MP25\n\nKSHAREID values in CR register are different between plaforms.\nAdapt their definitions under flag condition.\n\nSigned-off-by: Maxime Méré \u003cmaxime.mere@foss.st.com\u003e\nChange-Id: I100591769dad4565237967ec0a4844a621534516\n" }, { "commit": "7dd90ad0a313c3e00eab4323414d119aaee4a1ce", "tree": "0983de1398980f540ef84a217fca6e95f15b6292", "parents": [ "32740206ca6b18a0d213f2d4ac76a049c6de0ec7" ], "author": { "name": "Maxime Méré", "email": "maxime.mere@foss.st.com", "time": "Wed Jan 24 14:50:43 2024" }, "committer": { "name": "Yann Gautier", "email": "yann.gautier@st.com", "time": "Tue Sep 29 16:36:05 2026" }, "message": "feat(st-crypto): check if SAES is already initialized\n\nThis patch checks if SAES has already been initialized to avoid\ninitializing it twice.\n\nSigned-off-by: Maxime Méré \u003cmaxime.mere@foss.st.com\u003e\nChange-Id: Icd635735ff85eadaf386c9205b8215d515615680\n" }, { "commit": "32740206ca6b18a0d213f2d4ac76a049c6de0ec7", "tree": "a97fcb4532f39dd4960be4d66ba2934abc8debab", "parents": [ "374dfb985e9cc3bce6c16d1b47614e4186adc5cb" ], "author": { "name": "Maxime Méré", "email": "maxime.mere@foss.st.com", "time": "Fri May 29 12:54:11 2026" }, "committer": { "name": "Yann Gautier", "email": "yann.gautier@st.com", "time": "Tue Sep 29 16:36:05 2026" }, "message": "fix(st-crypto): use static CLKDIV for RNG on MP2x platforms\n\nOn MP2x (MP25, MP23, MP21), the RNG kernel clock (rng_clk) is a fixed\n64MHz oscillator (clk_rcbsec) that is not exposed in the device tree.\nThe DT only provides the bus clock (hclk). The runtime call to\nclk_get_rate() was computing CLKDIV against the bus clock frequency\ninstead of the actual noise source clock, resulting in an incorrect\ndivider value programmed in RNG_CR[CLKDIV].\n\nReplace the runtime computation with a static divider value derived\nfrom the known 64MHz source for MP2x:\n- MP25/MP23: 64MHz \u003e\u003e 1 \u003d 32MHz (target \u003c\u003d 48MHz)\n- MP21: 64MHz \u003e\u003e 4 \u003d 4MHz (target \u003c\u003d 4MHz)\n\nKeep runtime computation for MP13 where stm32_rng.clock corresponds\nto the actual RNG kernel clock (RNG1_K), for which clk_get_rate()\nreturns the correct frequency.\n\nChange-Id: I1884f0cb3bc5ddd846cd38f052a3631aeeb61cd0\nSigned-off-by: Maxime Méré \u003cmaxime.mere@foss.st.com\u003e\n" }, { "commit": "374dfb985e9cc3bce6c16d1b47614e4186adc5cb", "tree": "6b6206d287c2d3a0794ef596e024f7bac73e75d8", "parents": [ "b9cc82f024b7841b7703db50d9e63f59d4ea3224" ], "author": { "name": "Nicolas Le Bayon", "email": "nicolas.le.bayon@foss.st.com", "time": "Mon Feb 03 13:07:17 2025" }, "committer": { "name": "Yann Gautier", "email": "yann.gautier@st.com", "time": "Tue Sep 29 16:36:05 2026" }, "message": "fix(st-crypto): increase RNG robustness for STM32MP21\n\nOn STM32MP21, enabling RNG starts the hardware execution of the BSEC\nHWBUS which will generate the DDRcrypt encryption key (RISAF4 for DDR).\nIt is crucial that no seed error occurs during this phase.\nReducing the RNG maximum noise clock frequency increase the RNG\nrobustness without impacting the general boot time.\n\nSigned-off-by: Nicolas Le Bayon \u003cnicolas.le.bayon@foss.st.com\u003e\nChange-Id: I2ae49be65bc20fdb234dccd7076411be2414673f\n" }, { "commit": "b9cc82f024b7841b7703db50d9e63f59d4ea3224", "tree": "029c28de61ba0eb302e5739d7866857be46fce32", "parents": [ "80d48762a7e8c271b69d8782a97863b2f2892c34" ], "author": { "name": "Maxime Méré", "email": "maxime.mere@foss.st.com", "time": "Fri Jan 31 17:08:55 2025" }, "committer": { "name": "Yann Gautier", "email": "yann.gautier@st.com", "time": "Tue Sep 29 16:36:05 2026" }, "message": "feat(st-crypto): improve RNG parameter for all platform\n\nThe value of RNG_NSCR registe could be improved according to IP version.\nSet a better value to improve the IP behavior.\n\nChange-Id: I4a4339f684a5ac6929e5ad9296be5749a53bab3d\nSigned-off-by: Maxime Méré \u003cmaxime.mere@foss.st.com\u003e\n" }, { "commit": "80d48762a7e8c271b69d8782a97863b2f2892c34", "tree": "b5c7961f6ee45a60109e45cffb3eac31c560f39a", "parents": [ "7a8ba4b3bfa400ee5cf499e3faec81c8c523d3bc" ], "author": { "name": "Nicolas Le Bayon", "email": "nicolas.le.bayon@foss.st.com", "time": "Wed Nov 27 10:36:25 2024" }, "committer": { "name": "Yann Gautier", "email": "yann.gautier@st.com", "time": "Tue Sep 29 16:36:05 2026" }, "message": "feat(st-crypto): manage RNG customization with device tree\n\nImplement an optional way of RNG configuration via the device tree which\nwill override default hard-coded one.\nIt concerns both NIST and health test configurations.\n\nSigned-off-by: Nicolas Le Bayon \u003cnicolas.le.bayon@foss.st.com\u003e\nChange-Id: Ie4525392b889784d6d4feb655b74b96a4c849257\n" }, { "commit": "7a8ba4b3bfa400ee5cf499e3faec81c8c523d3bc", "tree": "ae2286cc258a32fba9178be83f46c39a361c5382", "parents": [ "58bd918dce1e2831fbec252c0b2139d519a00d55" ], "author": { "name": "Nicolas Le Bayon", "email": "nicolas.le.bayon@foss.st.com", "time": "Tue Nov 26 17:28:59 2024" }, "committer": { "name": "Yann Gautier", "email": "yann.gautier@st.com", "time": "Tue Sep 29 16:36:05 2026" }, "message": "refactor(st-crypto): split RNG NIST configuration\n\nSeparate each RNG NIST configuration bit field and add a macro to\ncompute global value.\nRemove deprecated definitions.\nUse BIT_32 and GENMASK_32 macros, as they\u0027re adapted to 32 bit registers.\n\nSigned-off-by: Nicolas Le Bayon \u003cnicolas.le.bayon@foss.st.com\u003e\nChange-Id: I9db5f874c7e33cd41dc16b755b3cfdc5053fc995\n" }, { "commit": "58bd918dce1e2831fbec252c0b2139d519a00d55", "tree": "9c53ad78931856c0a62fc94de76134582442997b", "parents": [ "b4c0ebb333e31d973cdffb40eb672c254a0fbcd1", "84fe0d84e054e34c6f0e7a512abc552c6a20652c" ], "author": { "name": "Boyan Karatotev", "email": "boyan.karatotev@arm.com", "time": "Tue Sep 29 15:33:48 2026" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Tue Sep 29 15:33:48 2026" }, "message": "Merge changes I8ca47f0e,I2bbd0706,I459eb091,I845a6e15,I1e296cbb, ... into integration\n\n* changes:\n fix(k3low): use size_t for fwls index\n fix(k3low): set K3_SEC_PROXY_LITE to 0\n fix(arm): move ETHOSN_NPU flags to arm_common.mk\n fix(arm): move PLAT_TEST_SPM to arm_common.mk\n fix(arm): move JUNO_AARCH32_EL3_RUNTIME to arm_common.mk\n fix(build): manage ARM_RECOM_STATE_ID_ENC in Makefile\n fix(build): remove ARM_PLAT_MT in plat_arm.h\n" }, { "commit": "b4c0ebb333e31d973cdffb40eb672c254a0fbcd1", "tree": "e3b9a45b6cb4a274f5613fe6cf9e9d8cbfb28611", "parents": [ "19359dc064bcfbc32663a43a1e909c9776f11fa6", "8e6c0fbeb1c87911723635e2c649014fc2023833" ], "author": { "name": "Harrison Mutai", "email": "harrison.mutai@arm.com", "time": "Tue Sep 29 13:30:30 2026" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Tue Sep 29 13:30:30 2026" }, "message": "Merge changes I24a5aa93,I2dd2db30,Iaaccfbbf,Ib3923895 into integration\n\n* changes:\n refactor(build): remove obsolete path helpers\n refactor(build)!: remove `CPP` variable\n refactor(build)!: remove `AS` variable\n chore(build): remove grouped-target compatibility variable\n" }, { "commit": "8e6c0fbeb1c87911723635e2c649014fc2023833", "tree": "8d2eb4242fbc71b782e0ceb3e6aee381915816bc", "parents": [ "671b8d52a8bbaf5f2b3f64583fbe5033430681b9" ], "author": { "name": "Chris Kay", "email": "chris.kay@arm.com", "time": "Thu Sep 24 00:52:43 2026" }, "committer": { "name": "Chris Kay", "email": "chris.kay@arm.com", "time": "Tue Sep 29 10:52:05 2026" }, "message": "refactor(build): remove obsolete path helpers\n\nNative Windows builds are no longer supported and have not been for some\ntime, and these path helpers have no remaining callers. Remove them.\n\nChange-Id: I24a5aa93d87d8a266413736c3b7ccc5efc379864\nSigned-off-by: Chris Kay \u003cchris.kay@arm.com\u003e\n" }, { "commit": "671b8d52a8bbaf5f2b3f64583fbe5033430681b9", "tree": "24963017b90170364aa76714b499e1f508bf1ef5", "parents": [ "c7354368ff528919e8acc74aca91480c455fc5ef" ], "author": { "name": "Chris Kay", "email": "chris.kay@arm.com", "time": "Tue Sep 22 23:41:08 2026" }, "committer": { "name": "Chris Kay", "email": "chris.kay@arm.com", "time": "Tue Sep 29 10:52:05 2026" }, "message": "refactor(build)!: remove `CPP` variable\n\nBy convention, `CPP` names a C preprocessor command like `cpp -E`, but\nTF-A requires `CPP` to name a GCC-style compiler driver like `cc`.\n\nBuild environments which follow this convention, like Nix and Yocto,\ntherefore encounter build failures without additional workarounds, and\nmust instead explicitly override `CPP` to satisfy TF-A\u0027s unconventional\nexpectations.\n\nInstead, use the selected C compiler for preprocessing C, remove the\nseparate C preprocessor configuration, and remove the corresponding\nworkaround from the Nix flake.\n\nThe expected compatibility impact of this is fairly low: integrations\nthat override `CPP` solely to use the selected C compiler no longer need\nto work around this behaviour. However, removing the ability to select a\nseparate driver for C preprocessing does technically remain a breaking\nchange to our public build interface\n\nBREAKING-CHANGE: `CPP` and `HOSTCPP` no longer select the driver used\n for preprocessing C. C preprocessing instead now uses the compiler\n drivers selected by `CC` and `HOSTCC`, respectively.\n\nChange-Id: I2dd2db30312d6060aa4acf211dff81e392dbfa98\nSigned-off-by: Chris Kay \u003cchris.kay@arm.com\u003e\n" }, { "commit": "c7354368ff528919e8acc74aca91480c455fc5ef", "tree": "7a662d6e2fb7b7fdeb8fbdc4bd35a3185489edba", "parents": [ "f8c260fa9ad050394e1879cab89f3be841f92407" ], "author": { "name": "Chris Kay", "email": "chris.kay@arm.com", "time": "Tue Sep 22 23:28:22 2026" }, "committer": { "name": "Chris Kay", "email": "chris.kay@arm.com", "time": "Tue Sep 29 10:52:00 2026" }, "message": "refactor(build)!: remove `AS` variable\n\nBy convention, `AS` names an assembler command like `as`, but TF-A\nrequires `AS` to name a GCC-style compiler driver like `cc`.\n\nBuild environments which follow this convention, like Nix and Yocto,\ntherefore encounter build failures without additional workarounds, and\nmust instead explicitly override `AS` to satisfy TF-A\u0027s unconventional\nexpectations.\n\nInstead, use the selected C compiler for assembly, remove the separate\nassembly configuration, and remove the corresponding workaround from the\nNix flake.\n\nThe expected compatibility impact of this is fairly low: integrations\nthat override `AS` solely to use the selected C compiler no longer need\nto work around this behaviour. However, removing the ability to select a\nseparate driver for assembly does technically remain a breaking change\nto our public build interface\n\nBREAKING-CHANGE: `AS` and `HOSTAS` no longer select the driver used for\n assembly. Assembly instead now uses the compiler drivers selected by\n `CC` and `HOSTCC`, respectively.\n\nChange-Id: Iaaccfbbf98c5042c3d12435be035e3dfac115f39\nSigned-off-by: Chris Kay \u003cchris.kay@arm.com\u003e\n" }, { "commit": "540134b53d7892f2383739aad5f0b2a2069134c1", "tree": "14731e3bb86cec6540a958d43a5a068ff1f52827", "parents": [ "2f95189f27ad73f37b0542d89186883c7e360bfa" ], "author": { "name": "Johann Scott", "email": "johann.scott@arm.com", "time": "Wed Aug 19 14:13:34 2026" }, "committer": { "name": "Boyan Karatotev", "email": "boyan.karatotev@arm.com", "time": "Tue Sep 29 08:55:35 2026" }, "message": "feat(cpufeat): complete branch recording at EL3\n\nThis patch provides an exception-based mechanism to dump the branch\nrecord buffer (BRB) whenever it is full, avoiding a loss of profiling\ndata. Configuration of this required a PMU counter to be reserved for\nthe duration of recording. It can be used as follows:\n\nbrbe_start_recording();\n\u003cel3 code to be profiled\u003e\nbrbe_stop_recording();\n\nChange-Id: Ib49aae42ee05f1b42c754da34faf8fa1b2d76d4e\nSigned-off-by: Johann Scott \u003cjohann.scott@arm.com\u003e\n" }, { "commit": "2f95189f27ad73f37b0542d89186883c7e360bfa", "tree": "014b035ea66a9dc98c69389c4bdb2292e9c08d9d", "parents": [ "a32709691ed3eebf5b520f7e27eba428db5eba60" ], "author": { "name": "Johann Scott", "email": "johann.scott@arm.com", "time": "Wed Aug 19 14:08:25 2026" }, "committer": { "name": "Boyan Karatotev", "email": "boyan.karatotev@arm.com", "time": "Tue Sep 29 08:55:01 2026" }, "message": "refactor(cpufeat): modularised EL3 sync exceptions\n\nThis patch modifies handle_el3_sync_exception to dispatch exception\nhandlers based off the value of ESR_EL3, with the proviso that said\nhandlers return on success or panic otherwise.\n\nChange-Id: I198a8b8c546fcbda29ed0f42ddb9e292842e7faa\nSigned-off-by: Johann Scott \u003cjohann.scott@arm.com\u003e\n" }, { "commit": "a32709691ed3eebf5b520f7e27eba428db5eba60", "tree": "bb50deda752671d49e2c09c1253bbb320464ce91", "parents": [ "42c2225866b6ef39095c9476fd346fd7ad5f4bae" ], "author": { "name": "Johann Scott", "email": "johann.scott@arm.com", "time": "Wed Aug 26 12:38:51 2026" }, "committer": { "name": "Boyan Karatotev", "email": "boyan.karatotev@arm.com", "time": "Tue Sep 29 08:55:01 2026" }, "message": "fix: correct ISS_DFSC_WIDTH\n\nPreviously, this was set to 5 whilst the actual width of the field is 6.\nSee \"ISS encoding for an exception from a Data Abort\" in the Arm ARM.\n\nChange-Id: I979cbe59943138ae8405215a7c276c0571cc5458\nSigned-off-by: Johann Scott \u003cjohann.scott@arm.com\u003e\n" }, { "commit": "42c2225866b6ef39095c9476fd346fd7ad5f4bae", "tree": "7a6dec4ad574b9650a62b576ecc4048e0c29527b", "parents": [ "19359dc064bcfbc32663a43a1e909c9776f11fa6" ], "author": { "name": "Johann Scott", "email": "johann.scott@arm.com", "time": "Mon Aug 17 10:42:10 2026" }, "committer": { "name": "Boyan Karatotev", "email": "boyan.karatotev@arm.com", "time": "Tue Sep 29 08:55:01 2026" }, "message": "refactor(rme): panic on non-recoverable exception\n\nPrevious behaviour was to return an invalid address and then report an\nunhandled exception. Panicking is a more appropriate response, as the\nexception is handled as a failure. This also removes the extraneous\ninvalid address return, as elr_el3 is overwritten in the handler.\n\nChange-Id: Ic60963df1b14b100ac7497a3129ce717cb358cb2\nSigned-off-by: Johann Scott \u003cjohann.scott@arm.com\u003e\n" }, { "commit": "19359dc064bcfbc32663a43a1e909c9776f11fa6", "tree": "3ff4a2c5eb7c01475c8b54cd4bd1761986fea348", "parents": [ "1e7d7a79a744f8ede5dabe3cee36f52e7c58b686", "d4c5f9b6bb651e82fb4b37cbaf2f29cd9a3d0a71" ], "author": { "name": "Manish Pandey", "email": "manish.pandey2@arm.com", "time": "Mon Sep 28 15:59:33 2026" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Mon Sep 28 15:59:33 2026" }, "message": "Merge \"fix(spmd): allow TL manifest processing with RESET_TO_BL31\" into integration" }, { "commit": "1e7d7a79a744f8ede5dabe3cee36f52e7c58b686", "tree": "53ef9ee918cfaf1038520d01a723986bb45b4487", "parents": [ "b80ffcc80f23d3efe41aee0eeb36cd2b0b837aca", "ebe0f79ae132210b620d260fc2d2e27639f769bb" ], "author": { "name": "Boyan Karatotev", "email": "boyan.karatotev@arm.com", "time": "Mon Sep 28 15:58:28 2026" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Mon Sep 28 15:58:28 2026" }, "message": "Merge \"docs(maintainers): add Altera/Intel platform docs and update maintainers\" into integration" }, { "commit": "b80ffcc80f23d3efe41aee0eeb36cd2b0b837aca", "tree": "8a4cd0dad81908f2f1328b3e39c131093a6dd41d", "parents": [ "36e5adcccf55aa232ca812d6635e5b919a0f8339", "ea759212c7a26bd5254cd46f4f1e9e55441b824a" ], "author": { "name": "Manish Pandey", "email": "manish.pandey2@arm.com", "time": "Mon Sep 28 15:17:55 2026" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Mon Sep 28 15:17:55 2026" }, "message": "Merge \"refactor(cpus): rename Canyon to C2-Ultra\" into integration" }, { "commit": "36e5adcccf55aa232ca812d6635e5b919a0f8339", "tree": "21694c1e23eea43bf44f383d614fe88a289ab03c", "parents": [ "331ceb88010adb79afb31f20f7d560c580d2843d", "2a9393c1499b7ec9b6f880153adb134a3df9a331" ], "author": { "name": "Harrison Mutai", "email": "harrison.mutai@arm.com", "time": "Mon Sep 28 15:02:11 2026" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Mon Sep 28 15:02:11 2026" }, "message": "Merge changes from topic \"imx952_support\" into integration\n\n* changes:\n feat(imx952): runtime detect GPIO2\n feat(imx952): add logic of detecting SGMII wakeup\n feat(imx952): enable OP-TEE support for i.MX952\n feat(imx952): add CRRM support\n feat(imx952): add iMX952 initial support\n docs(imx9): add imx952 as valid PLAT target\n docs(maintainers): add imx952 platform path\n build(changelog): add imx952 scope\n fix(imx9): fix the recursion in included headers\n" }, { "commit": "2a9393c1499b7ec9b6f880153adb134a3df9a331", "tree": "598d03179da5dce25e7626e66101961998548c4c", "parents": [ "6766971a0d8821ab5dc6d641a1b9e555f0309aa7" ], "author": { "name": "Peng Fan", "email": "peng.fan@nxp.com", "time": "Mon Jan 12 09:35:53 2026" }, "committer": { "name": "Jacky Bai", "email": "ping.bai@nxp.com", "time": "Mon Sep 28 15:00:25 2026" }, "message": "feat(imx952): runtime detect GPIO2\n\nGPIO2 may not be owned by A55 SW, so check the CPU_PER_LPI_IDX_GPIO2 and\ntake the result as permission gate. Based on the result, handle or\nbypass GPIO2.\n\nSigned-off-by: Peng Fan \u003cpeng.fan@nxp.com\u003e\nReviewed-by: Jacky Bai \u003cping.bai@nxp.com\u003e\nChange-Id: I9afde79cf1b99f1c05e3d12307c0d2b314c15176\n" }, { "commit": "6766971a0d8821ab5dc6d641a1b9e555f0309aa7", "tree": "ebaa146e5b2361159d03e7aa6a722e2fc7b4fc01", "parents": [ "3f674ce99485cee5f69c177909be2c4e357aee40" ], "author": { "name": "Peng Fan", "email": "peng.fan@nxp.com", "time": "Thu May 21 14:15:08 2026" }, "committer": { "name": "Jacky Bai", "email": "ping.bai@nxp.com", "time": "Mon Sep 28 15:00:25 2026" }, "message": "feat(imx952): add logic of detecting SGMII wakeup\n\nOn i.MX952, NETC_IREC_PCI_INT_X0 (304) and X1 (305) share the\nsame IRQ_MASK index (9). Add wakeup irq detection with GPIO wakeup\nbehavior for SGMII.\n\nSigned-off-by: Peng Fan \u003cpeng.fan@nxp.com\u003e\nReviewed-by: Jacky Bai \u003cping.bai@nxp.com\u003e\nTested-by: Clark Wang \u003cxiaoning.wang@nxp.com\u003e\nChange-Id: Iec68a17ecd57934fdf9e21ef2ef294f7120677d9\n" }, { "commit": "3f674ce99485cee5f69c177909be2c4e357aee40", "tree": "3bec41bd7777a184d99e68fa2db541c37a8a8200", "parents": [ "152c45255b30d5f5dbe38917d8a8918bb6fc0008" ], "author": { "name": "Sahil Malhotra", "email": "sahil.malhotra@nxp.com", "time": "Wed May 14 08:41:18 2025" }, "committer": { "name": "Jacky Bai", "email": "ping.bai@nxp.com", "time": "Mon Sep 28 15:00:25 2026" }, "message": "feat(imx952): enable OP-TEE support for i.MX952\n\nEnable OP-TEE support on i.MX952\n\nSigned-off-by: Sahil Malhotra \u003csahil.malhotra@nxp.com\u003e\nSigned-off-by: Jacky Bai \u003cping.bai@nxp.com\u003e\nReviewed-by: Ye Li \u003cye.li@nxp.com\u003e\nReviewed-by: Peng Fan \u003cpeng.fan@nxp.com\u003e\nChange-Id: Ie97d7dbe2dca51ece98f341b2961d83a1821957f\n" }, { "commit": "152c45255b30d5f5dbe38917d8a8918bb6fc0008", "tree": "5e8e2bfbe9454ef63b3ae0e3e81a5d106cf9b77c", "parents": [ "9721581ef0f7e30613076b8ff3161dd9aa31bcc5" ], "author": { "name": "Ye Li", "email": "ye.li@nxp.com", "time": "Tue Aug 26 05:51:00 2025" }, "committer": { "name": "Jacky Bai", "email": "ping.bai@nxp.com", "time": "Mon Sep 28 15:00:03 2026" }, "message": "feat(imx952): add CRRM support\n\nKeep wakeupmix on during system sleep to avoid XSPI setting\nlost. User need to set IMX_CRRM\u003d1 in build option.\n\nSigned-off-by: Ye Li \u003cye.li@nxp.com\u003e\nSigned-off-by: Jacky Bai \u003cping.bai@nxp.com\u003e\nReviewed-by: Peng Fan \u003cpeng.fan@nxp.com\u003e\nChange-Id: I012e32a2ce1b3a06ba2816f6a0d0e5f9b7747e7c\n" }, { "commit": "f8c260fa9ad050394e1879cab89f3be841f92407", "tree": "b9afd2aef7ef37063e63e64f5428178b4cfe11e0", "parents": [ "331ceb88010adb79afb31f20f7d560c580d2843d" ], "author": { "name": "Chris Kay", "email": "chris.kay@arm.com", "time": "Thu Sep 24 00:51:05 2026" }, "committer": { "name": "Chris Kay", "email": "chris.kay@arm.com", "time": "Mon Sep 28 14:53:29 2026" }, "message": "chore(build): remove grouped-target compatibility variable\n\nOur prerequisites specify GNU Make 4.3 is required to build TF-A; the\nlatest Ubuntu release an older version appears in was 20.04, which is no\nlonger generally supported as of May 2025.\n\nChange-Id: Ib3923895c88c88867260212afab4aa8094e224ca\nSigned-off-by: Chris Kay \u003cchris.kay@arm.com\u003e\n" }, { "commit": "ebe0f79ae132210b620d260fc2d2e27639f769bb", "tree": "a3151f7934c8a57eec2140e304860558aa668def", "parents": [ "d24f9062997888a0c32d445c97a008e2ba87b000" ], "author": { "name": "Jit Loon Lim", "email": "jit.loon.lim@altera.com", "time": "Fri Aug 14 01:17:47 2026" }, "committer": { "name": "Jit Loon Lim", "email": "jit.loon.lim@altera.com", "time": "Mon Sep 28 12:21:32 2026" }, "message": "docs(maintainers): add Altera/Intel platform docs and update maintainers\n\nAdd platform documentation for Agilex3, Agilex72, and Agilex5, and\nupdate the Altera/Intel maintainers list to reflect the current roles\nand documentation paths.\n\nChange-Id: Iaed9b5e8e73fe8c00de5d3514d25070f06334eb1\nSigned-off-by: Jit Loon Lim \u003cjit.loon.lim@altera.com\u003e\n\n\n" }, { "commit": "331ceb88010adb79afb31f20f7d560c580d2843d", "tree": "ff41c05fa17e5acc15276ab08d61d7ff9085a566", "parents": [ "d24f9062997888a0c32d445c97a008e2ba87b000", "420b4f067adbc2ed1220a8190154339c6df2d123" ], "author": { "name": "Boyan Karatotev", "email": "boyan.karatotev@arm.com", "time": "Mon Sep 28 11:47:26 2026" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Mon Sep 28 11:47:26 2026" }, "message": "Merge \"docs(qti): add power driver maintainer\" into integration" }, { "commit": "84fe0d84e054e34c6f0e7a512abc552c6a20652c", "tree": "9d51a93dd65263dc75d30131839b37103b1c1b1c", "parents": [ "4aaa10e87e02b4252a6a822a161f4702cd2632d6" ], "author": { "name": "Yann Gautier", "email": "yann.gautier@st.com", "time": "Fri Sep 25 12:28:31 2026" }, "committer": { "name": "Yann Gautier", "email": "yann.gautier@st.com", "time": "Mon Sep 28 11:46:56 2026" }, "message": "fix(k3low): use size_t for fwls index\n\nThe index of the fwls table should be size_t as it is compared to an\nARRAY_SIZE. And as it is a table index, it cannot be negative. Change\n`int i` to `size_t i`. This was found when enabling -Wsign-compare.\n\nChange-Id: I8ca47f0e376d61829848b2281480ffd38e6b49c4\nSigned-off-by: Yann Gautier \u003cyann.gautier@st.com\u003e\n" }, { "commit": "4aaa10e87e02b4252a6a822a161f4702cd2632d6", "tree": "782c9d09fd8aa9172f89bde99f2cad189566092e", "parents": [ "5a107141a302462398f24ec56b33575a253096e0" ], "author": { "name": "Yann Gautier", "email": "yann.gautier@st.com", "time": "Fri Sep 25 12:25:03 2026" }, "committer": { "name": "Yann Gautier", "email": "yann.gautier@st.com", "time": "Mon Sep 28 11:46:56 2026" }, "message": "fix(k3low): set K3_SEC_PROXY_LITE to 0\n\nThis flag is used in drivers/ti/ti_sci/ti_sci_transport.h, which this\nplatform uses. But the platform k3low doesn\u0027t define the flag. Set it\nto 0 in platform.mk, and use add_define. This will avoid build error\nwhen -Wundef flag is set.\n\nChange-Id: I2bbd07069fee22fe4c8e45685797f0675af3c2f3\nSigned-off-by: Yann Gautier \u003cyann.gautier@st.com\u003e\n" }, { "commit": "5a107141a302462398f24ec56b33575a253096e0", "tree": "6e6cc1ad6b2d43bfde3abd421cbb91a245ff4a2b", "parents": [ "75eec1a72f0e55fe35c41d2c1c06cfdba3340dae" ], "author": { "name": "Yann Gautier", "email": "yann.gautier@st.com", "time": "Fri Sep 25 14:05:05 2026" }, "committer": { "name": "Yann Gautier", "email": "yann.gautier@st.com", "time": "Mon Sep 28 11:46:56 2026" }, "message": "fix(arm): move ETHOSN_NPU flags to arm_common.mk\n\nThose flags are used in several files that are used by platform that do\nnot use Ethos-N NPU. They should be managed in arm_common.mk, and set\nto 0 by default. Else some platforms fail to build when -Wundef flag is\nset.\n\nChange-Id: I459eb091b743b8f7284d9f42468ff73b71af0167\nSigned-off-by: Yann Gautier \u003cyann.gautier@st.com\u003e\n" }, { "commit": "75eec1a72f0e55fe35c41d2c1c06cfdba3340dae", "tree": "5a16b4b7b9bea2721effbd8a17526088253ac4c7", "parents": [ "c970f8c5276e11c06ba7c899c57d611260fba918" ], "author": { "name": "Yann Gautier", "email": "yann.gautier@st.com", "time": "Fri Sep 25 12:42:38 2026" }, "committer": { "name": "Yann Gautier", "email": "yann.gautier@st.com", "time": "Mon Sep 28 11:46:56 2026" }, "message": "fix(arm): move PLAT_TEST_SPM to arm_common.mk\n\nThis flag is used in several files that are used by other platforms than\nFVP. When -Wundef flag is set, there are build failures for several Arm\nplatforms (Corstone1000...). Move the add_define to arm_common.mk, and\nset the flag to 0 if it is not set.\n\nChange-Id: I845a6e15cbdfcb7121cd91fe9f77d78f59ceefb0\nSigned-off-by: Yann Gautier \u003cyann.gautier@st.com\u003e\n" }, { "commit": "c970f8c5276e11c06ba7c899c57d611260fba918", "tree": "164ce5d0cb0c004c8d59c1090271cfeaad385487", "parents": [ "8ba14448a3e8de5570af64b3cc8f4cc792c0ebe8" ], "author": { "name": "Yann Gautier", "email": "yann.gautier@st.com", "time": "Fri Sep 25 12:32:17 2026" }, "committer": { "name": "Yann Gautier", "email": "yann.gautier@st.com", "time": "Mon Sep 28 11:46:56 2026" }, "message": "fix(arm): move JUNO_AARCH32_EL3_RUNTIME to arm_common.mk\n\nThis flag is used in several files that are used by other platforms than\nJuno. When -Wundef flag is set, there are build failures for several Arm\nplatforms (FVP, Corstone1000...). Move the add_define to arm_common.mk,\nand set the flag to 0 if it is not set.\n\nChange-Id: I1e296cbbe4ba10a2160749e3c60d5eaf188403ba\nSigned-off-by: Yann Gautier \u003cyann.gautier@st.com\u003e\n" }, { "commit": "8ba14448a3e8de5570af64b3cc8f4cc792c0ebe8", "tree": "045989fca366b41293be3bc0ee9bc1314e01d798", "parents": [ "df5f1b47a52bbe5342ab8ad8bac8038892ec131d" ], "author": { "name": "Yann Gautier", "email": "yann.gautier@st.com", "time": "Fri Sep 25 12:06:08 2026" }, "committer": { "name": "Yann Gautier", "email": "yann.gautier@st.com", "time": "Mon Sep 28 11:46:54 2026" }, "message": "fix(build): manage ARM_RECOM_STATE_ID_ENC in Makefile\n\nSome platforms other than Arm\u0027s can include files that use the flag:\nARM_RECOM_STATE_ID_ENC. As it is not defined, it triggers a build error\nwhen -Wundef flag is set.\nManage the flag globally, and set it to 0 by default.\nThe documentation for the flag is moved from a dedicated Arm doc to\nthe generic build-options.rst file.\n\nChange-Id: Idfeb338c673635afa396b1bbe6fb9ab8c3d6bb50\nSigned-off-by: Yann Gautier \u003cyann.gautier@st.com\u003e\n" }, { "commit": "df5f1b47a52bbe5342ab8ad8bac8038892ec131d", "tree": "1115050fc2d5b7cfb0f155520157f2ce6d9a3764", "parents": [ "db7c3c8a7c935f8c33a81f929eba66e2b9d00387" ], "author": { "name": "Yann Gautier", "email": "yann.gautier@st.com", "time": "Fri Sep 25 11:56:27 2026" }, "committer": { "name": "Yann Gautier", "email": "yann.gautier@st.com", "time": "Mon Sep 28 11:45:47 2026" }, "message": "fix(build): remove ARM_PLAT_MT in plat_arm.h\n\nThe flag is used around plat_arm_get_cpu_pe_count() definition. This\nis not really required, even if the function is not used. And it avoids\na build warning when -Wundef flag is enabled.\n\nChange-Id: Ie7bee7116fb95e7f4a4659a6e8aad4785d0f7fa2\nSigned-off-by: Yann Gautier \u003cyann.gautier@st.com\u003e\n" }, { "commit": "d24f9062997888a0c32d445c97a008e2ba87b000", "tree": "9c9d3c0569cc8df1852ed2c36872dccf63be3aab", "parents": [ "db7c3c8a7c935f8c33a81f929eba66e2b9d00387", "7953d9aec7c570f4e3fc0634db5d1f728b24e5e5" ], "author": { "name": "Manish V Badarkhe", "email": "manish.badarkhe@arm.com", "time": "Mon Sep 28 09:48:56 2026" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Mon Sep 28 09:48:56 2026" }, "message": "Merge changes from topic \"hm/firme-att\" into integration\n\n* changes:\n feat(rdv3): add FIRME attestation platform hooks\n fix(rse): validate reply output sizes\n feat(rse): add non-blocking support to rse_comms\n feat(mhu): add non-blocking MHU receive support\n feat(psa): implement initial attestation client\n feat(psa): preserve blocking wrapper semantics\n feat(psa): support non-blocking attestation calls\n feat(psa): add non-blocking call semantics\n feat(firme): enable serialization of attest reqs\n feat(fvp): wire in FIRME attestation service\n feat(bl31): relax GPF hardened write alignment rule\n feat(firme): introduce FIRME attestation service\n chore: remove stale error code references\n" }, { "commit": "db7c3c8a7c935f8c33a81f929eba66e2b9d00387", "tree": "b81c9f38a3738bbba568a9d2831c55f2a9992387", "parents": [ "9599954cafaf7f1a0d8240242349db972b512150", "425d988f165cfa1be6ee019e589cedefe91c1a98" ], "author": { "name": "Boyan Karatotev", "email": "boyan.karatotev@arm.com", "time": "Mon Sep 28 08:43:14 2026" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Mon Sep 28 08:43:14 2026" }, "message": "Merge \"feat(altera): add Agilex72 platform base enablement\" into integration" }, { "commit": "ea759212c7a26bd5254cd46f4f1e9e55441b824a", "tree": "0df6d1ce9b2af4d7a2b02124b898a87bcd124607", "parents": [ "d2a8287d34fa4571e6e68204f903ac8c2a43ed5d" ], "author": { "name": "Antal Bánovics", "email": "antal.banovics@arm.com", "time": "Wed Sep 23 16:21:26 2026" }, "committer": { "name": "Antal Bánovics", "email": "antal.banovics@arm.com", "time": "Mon Sep 28 07:01:26 2026" }, "message": "refactor(cpus): rename Canyon to C2-Ultra\n\nRename the CPU implementation and register definitions to C2-Ultra\n\nAdd TRM and SDEN references to the CPU source file.\n\nChange-Id: I8f7202ed4d81f2912fe58f1dbb78906edeae93a7\nSigned-off-by: Antal Bánovics \u003cantal.banovics@arm.com\u003e\nLTS-candidate: yes\n" }, { "commit": "c5450ae975e489af353c956c60c48ffa23473bae", "tree": "4be8591402c4315e039b9c0b1d778839f9d50a19", "parents": [ "29fd3adae52dcc94833f9f7612d16ac9d3022012" ], "author": { "name": "Dinesh Choudhary", "email": "idinesh@qti.qualcomm.com", "time": "Fri Sep 25 18:19:23 2026" }, "committer": { "name": "Dinesh Choudhary", "email": "idinesh@qti.qualcomm.com", "time": "Fri Sep 25 18:21:40 2026" }, "message": "fix(qti): correct power driver init sequence\n\nCorrect the BL31 power driver init sequence so each driver runs only\nafter the state it consumes is ready.\n\nRPMh is initialized first because it waits for AOP boot completion.\nAOP publishes the command DB data, so this gates later command DB reads.\n\nCommand DB runs next to validate and cache the AOP-published resource\nmetadata before other drivers query it.\n\nPower utils follows command DB because it builds its rail-level tables\nfrom command DB aux data.\n\nPDC follows command DB because its TCS setup resolves RPMh resource\naddresses through cmd_db_query_addr().\n\nTest: make PLAT\u003dlemans_evk SPD\u003dopteed DEBUG\u003d1 bl31\n\nChange-Id: Icf3ca6d46d7f758238517fe2edfe441e4984bf3a\nSigned-off-by: Dinesh Choudhary \u003cidinesh@qti.qualcomm.com\u003e\n" }, { "commit": "420b4f067adbc2ed1220a8190154339c6df2d123", "tree": "b01b794f1d37721a880ebf9910b6317328c7dc04", "parents": [ "9599954cafaf7f1a0d8240242349db972b512150" ], "author": { "name": "Dinesh Choudhary", "email": "idinesh@qti.qualcomm.com", "time": "Fri Sep 25 10:59:08 2026" }, "committer": { "name": "Dinesh Choudhary", "email": "idinesh@qti.qualcomm.com", "time": "Fri Sep 25 10:59:08 2026" }, "message": "docs(qti): add power driver maintainer\n\nAdd a dedicated QTI power drivers code-owner entry for the\nRPMh, command DB, power utilities and PDC driver directories.\n\nThis narrows reviewer discovery for changes touching these shared\npower-management components while keeping the broader QTI platform\nownership entry in place.\n\nChange-Id: I53f526759f4db9f7a7bd0805a4497e84e351360c\nSigned-off-by: Dinesh Choudhary \u003cidinesh@qti.qualcomm.com\u003e\n" }, { "commit": "70132f5146b7c3183c9683d3101992dfb38dca0e", "tree": "465c92206219ea0940514f3841bda079aa2d1270", "parents": [ "9646baa93573dc8895b1014b4999546c013eef38" ], "author": { "name": "Tyler Baker", "email": "tyler.baker@oss.qualcomm.com", "time": "Fri Sep 25 09:53:54 2026" }, "committer": { "name": "Sumit Garg", "email": "sumit.garg@oss.qualcomm.com", "time": "Fri Sep 25 10:25:23 2026" }, "message": "feat(qti): start CPUCP from BL31 on Lemans\n\nOn Lemans XBL loads the CPUCP firmware into EPSS memory but leaves it\nhalted, and nothing in TF-A starts it. The EPSS therefore stays\ndisabled and Linux loses cpufreq and L3 scaling:\n\n osm-l3 18590000.interconnect: error hardware not enabled\n platform 18591000.cpufreq: deferred probe pending: qcom-cpufreq-hw:\n Failed to find icc paths\n\nInstantiate the common hoya CPUCP start sequence for Lemans and wire it\ninto the BL31 cold boot: lemans/cpucp_config.c supplies the APSS clocks,\nCPR fuse tables and interface version 2 chip identification, the\nclock-domain init table is collapsed to the CPUCP-started variant, and\nthe common BL31 setup calls qti_cpucp_init().\n\nTested on the IQ-9075 EVK: all 8 CPUs come online and cpufreq-hw probes\nwith 14 OPPs per cluster, reporting every requested OPP as with the\nstock firmware.\n\nChange-Id: I4a75b22ad9c68be29d4a9eb0931b2b38633679dd\nAssisted-by: Claude:claude-opus-5-5\nSigned-off-by: Tyler Baker \u003ctyler.baker@oss.qualcomm.com\u003e\nSigned-off-by: Sumit Garg \u003csumit.garg@oss.qualcomm.com\u003e\n" }, { "commit": "9646baa93573dc8895b1014b4999546c013eef38", "tree": "12b9d1ecfb36c72809c5c09253dd400d1666cef2", "parents": [ "9599954cafaf7f1a0d8240242349db972b512150" ], "author": { "name": "Tyler Baker", "email": "tyler.baker@oss.qualcomm.com", "time": "Fri Sep 25 09:53:03 2026" }, "committer": { "name": "Sumit Garg", "email": "sumit.garg@oss.qualcomm.com", "time": "Fri Sep 25 10:19:15 2026" }, "message": "feat(qti): add common hoya CPUCP start infrastructure\n\nThe CPUCP start sequence is common across hoya SoCs; only the fuse\ntables, SoC identification and a few parameters differ. Add it as a\ntarget-agnostic driver so each SoC can share it instead of duplicating\nthe sequence: hoya/cpucp_start.c implements qti_cpucp_init() and\ncpucp_config.h describes the per-target data a SoC supplies through\nstruct cpucp_config. cpucp.h gains an inline no-op stub of\nqti_cpucp_init() so platforms without the driver need no build guard.\n\nNo SoC wires this in yet; the first target follows.\n\nChange-Id: I002056f5053e08dcc02dc9bbae0e8ebba1225b5f\nAssisted-by: Claude:claude-opus-5-5\nSigned-off-by: Tyler Baker \u003ctyler.baker@oss.qualcomm.com\u003e\nSigned-off-by: Sumit Garg \u003csumit.garg@oss.qualcomm.com\u003e\n" }, { "commit": "9599954cafaf7f1a0d8240242349db972b512150", "tree": "1921efd9188f0dc4a4ad7aeea7e0b6730526279e", "parents": [ "724becadda27f6638e0f6a0b70214892e68a72b2", "7ba6836503e9a059eb145c8fa4159dc5d3ad721e" ], "author": { "name": "Harrison Mutai", "email": "harrison.mutai@arm.com", "time": "Fri Sep 25 09:07:39 2026" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Fri Sep 25 09:07:39 2026" }, "message": "Merge \"docs: fix SMC validation framework usage example\" into integration" }, { "commit": "724becadda27f6638e0f6a0b70214892e68a72b2", "tree": "a2c8c8d7c1f628efe929f6f10f4391062f70559a", "parents": [ "29fd3adae52dcc94833f9f7612d16ac9d3022012", "97067a3f877d44e3bc473ce0b862b2e36c476e50" ], "author": { "name": "Boyan Karatotev", "email": "boyan.karatotev@arm.com", "time": "Fri Sep 25 07:38:07 2026" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Fri Sep 25 07:38:07 2026" }, "message": "Merge changes from topic \"tf-a-nix-flake\" into integration\n\n* changes:\n docs(flake): explain package selection and source snapshots\n build(flake): extract firmware builder\n build(flake): install debugging artifacts\n build(flake): install FVP device trees\n build(flake): use `stdenv`\u0027s toolchain variables\n build(flake): rely on default environment settings\n build(flake): use structured Make flags\n build(flake): use default Make target\n build(flake): derive package version from source\n" }, { "commit": "425d988f165cfa1be6ee019e589cedefe91c1a98", "tree": "8ae3b8b60507c2d2ecf2a64900ed0d62f004f855", "parents": [ "c09c06e68d1125269045a8c108d3e47529fcdd1f" ], "author": { "name": "Jit Loon Lim", "email": "jit.loon.lim@altera.com", "time": "Thu Aug 06 10:50:35 2026" }, "committer": { "name": "Jit Loon Lim", "email": "jit.loon.lim@altera.com", "time": "Thu Sep 24 23:10:03 2026" }, "message": "feat(altera): add Agilex72 platform base enablement\n\nIntroduce Agilex72 BL2/BL31 platform enablement including GICv4,\nA720/A520 SMP product naming, Simics bring-up fixes, direct SD boot,\nv9 GPPLL clock-manager FSBL bring-up, and MCSR mailbox support\nrequired for HPS-SDM communication.\n\nAlso align the shared Altera NAND init API to nand_init(void) and\nupdate the Agilex3 call site so PLAT\u003dagilex3 remains buildable.\nPSCI now uses shared PWRMGR_* aliases; wire those (and cache\nheaders) into Agilex3 plat_def so existing platforms still build.\nGuard Agilex3 cache prototypes with __ASSEMBLER__ so plat_def can be\nincluded from assembly.\nKeep Agilex3 ncore CCU bases and noc_fw programming, and the\nupstream combo-PHY SDMMC DFI select. Agilex72 uses its own CCU\nmap and handoff-based DFI selection.\n\nAddress review feedback on this change:\n- rename plat_flash_* to altera_plat_flash_*\n- drop commented-out / unused bring-up stubs (incl. empty mmc stub)\n- switch Agilex72 to USE_GIC_DRIVER\u003d3\n- rewrite cache helpers in C using arch helpers\n- use utils_def EXTRACT/MASK for IOSSM fields\n- trim commented system-manager defines; clarify PSCI vs RMR_EL3\n- fix A720/A520 comments, enable FEATURE_DETECTION, drop unused evals\n- add Agilex72 code owner in docs/about/maintainers.rst\n- fix include order in bl31_plat_setup.c for static checks\n- cast EXTRACT() log args to fix -Werror\u003dformat on aarch64\n- restore Linux BL33/DTB build defines removed during review cleanup\n- provide the GICv3 MPIDR-to-core-position topology hook\n- define the default UART and fix release RESET_TO_BL31 compilation\n- drop redundant eval around assert_boolean/add_defines calls\n- remove stale bring-up markers and make the memcpy include explicit\n- drop leftover commented-out stubs; silence checkpatch long-line warning\n- preserve the upper CLUSTERECTLR_EL1 bits when masking bit 14\n- drop a dead ddr init prototype and duplicate register defines\n- rename the copied AGX5_ pinmux symbols to AGX72_\n\nxSPI flash boot and Config DMA remain deferred to a follow-up commit.\n\nChange-Id: If7b51026af7f685f51aad5ed0140240afdd7f721\nSigned-off-by: Jit Loon Lim \u003cjit.loon.lim@altera.com\u003e\nSigned-off-by: Poh San Ng \u003cpoh.san.ng@altera.com\u003e\nSigned-off-by: Bryan Chan Jia Ching \u003cbryan.chan@altera.com\u003e\nSigned-off-by: Yong Zi Hao \u003czi.hao.yong@altera.com\u003e\n\n" }, { "commit": "29fd3adae52dcc94833f9f7612d16ac9d3022012", "tree": "1432aa9d0a1c4b2d9cbce4bb4a997c2cf02238a4", "parents": [ "c09c06e68d1125269045a8c108d3e47529fcdd1f", "547f3301f2233e65a0321fa43229a78f1f0a4455" ], "author": { "name": "Harrison Mutai", "email": "harrison.mutai@arm.com", "time": "Thu Sep 24 14:00:24 2026" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Thu Sep 24 14:00:24 2026" }, "message": "Merge \"feat(common): make NS range hook a mandatory porting interface\" into integration" }, { "commit": "7953d9aec7c570f4e3fc0634db5d1f728b24e5e5", "tree": "9f10d8d83e84506554f1704e3ba768262e50bd34", "parents": [ "8b66bfa9b5b9e91ae666f766577502ebc09843aa" ], "author": { "name": "Harrison Mutai", "email": "harrison.mutai@arm.com", "time": "Thu May 28 14:23:18 2026" }, "committer": { "name": "Harrison Mutai", "email": "harrison.mutai@arm.com", "time": "Thu Sep 24 13:48:32 2026" }, "message": "feat(rdv3): add FIRME attestation platform hooks\n\nWire RD-V3 into the FIRME attestation platform interface using the RSE\ninitial attestation client.\n\nThe platform retrieves the RSE platform token into a local buffer,\nreports the required shared-buffer page count, and serves the token back\nto FIRME callers in chunks.\n\nChange-Id: I38b62a7a68292dea8432b70ef418142a8ad697dc\nSigned-off-by: Harrison Mutai \u003charrison.mutai@arm.com\u003e\n" }, { "commit": "8b66bfa9b5b9e91ae666f766577502ebc09843aa", "tree": "b941095658693603121bd950b7859cb6959d2647", "parents": [ "625b3fba7ad53551d4e176af9f1bd8f341057d7b" ], "author": { "name": "Harrison Mutai", "email": "harrison.mutai@arm.com", "time": "Wed Aug 26 15:32:15 2026" }, "committer": { "name": "Harrison Mutai", "email": "harrison.mutai@arm.com", "time": "Thu Sep 24 13:48:32 2026" }, "message": "fix(rse): validate reply output sizes\n\nValidate reply headers and output lengths before processing RSE\nresponses.\n\nEnsure embedded outputs fit both the caller-provided buffers and the\nreceived mailbox payload before copying any data. Also validate\npointer-access reply sizes and reported output lengths.\n\nChange-Id: Ida82452f0b8c239d2c03853f1d1978560cebc997\nSigned-off-by: Harrison Mutai \u003charrison.mutai@arm.com\u003e\n" }, { "commit": "625b3fba7ad53551d4e176af9f1bd8f341057d7b", "tree": "8f53ba6a1e50feeff8576b6d73235eb11c3b2486", "parents": [ "4561e43ebfee5b8610100ab06da0c7524c75082d" ], "author": { "name": "Tamas Ban", "email": "tamas.ban@arm.com", "time": "Mon Sep 01 13:29:46 2025" }, "committer": { "name": "Harrison Mutai", "email": "harrison.mutai@arm.com", "time": "Thu Sep 24 13:48:32 2026" }, "message": "feat(rse): add non-blocking support to rse_comms\n\nIf reply takes too long to read then the underlying\ncomms implementation returns after a predefined time\nto avoid long running blocking operations.\n\nChange-Id: I9e61bbf2c7f9c058d5b3db7a6cbadc6ae0209c50\nSigned-off-by: Tamas Ban \u003ctamas.ban@arm.com\u003e\n" }, { "commit": "4561e43ebfee5b8610100ab06da0c7524c75082d", "tree": "4ec13667986d5360f08bbc5d90b087110516e6e0", "parents": [ "f892a74f3564a696cd934d5736fe38b723f43a26" ], "author": { "name": "Tamas Ban", "email": "tamas.ban@arm.com", "time": "Mon Sep 01 13:24:45 2025" }, "committer": { "name": "Harrison Mutai", "email": "harrison.mutai@arm.com", "time": "Thu Sep 24 13:48:31 2026" }, "message": "feat(mhu): add non-blocking MHU receive support\n\nIf mhu_receive_data takes too long then it\nreturns after a predefined number of polling\ncycles to avoid long running blocking\noperations.\n\nChange-Id: Idc1853bd1da1a7bc949709269e3c133ec0f7bcbc\nSigned-off-by: Tamas Ban \u003ctamas.ban@arm.com\u003e\nCo-authored-by: Harrison Mutai \u003charrison.mutai@arm.com\u003e\n" }, { "commit": "f892a74f3564a696cd934d5736fe38b723f43a26", "tree": "f8d651080edf0719b6aa7d6e8529326564cc52db", "parents": [ "884f85be41bb403c69f1923b2febcdc140e2e121" ], "author": { "name": "Tamas Ban", "email": "tamas.ban@arm.com", "time": "Thu Aug 21 12:19:53 2025" }, "committer": { "name": "Harrison Mutai", "email": "harrison.mutai@arm.com", "time": "Thu Sep 24 13:48:31 2026" }, "message": "feat(psa): implement initial attestation client\n\nAdd a client implementation for the PSA Initial Attestation\nservice.\n\nChange-Id: I22303a40b34c2fa15517af0fc8f7805b7f00d4ad\nSigned-off-by: Tamas Ban \u003ctamas.ban@arm.com\u003e\n" }, { "commit": "884f85be41bb403c69f1923b2febcdc140e2e121", "tree": "d75085c8e2b24b0fe71d501864c83842992d2ce6", "parents": [ "127f7343d48f1e06b4e5d03da8269f37c21a05f6" ], "author": { "name": "Harrison Mutai", "email": "harrison.mutai@arm.com", "time": "Thu Jun 11 08:42:36 2026" }, "committer": { "name": "Harrison Mutai", "email": "harrison.mutai@arm.com", "time": "Thu Sep 24 13:48:31 2026" }, "message": "feat(psa): preserve blocking wrapper semantics\n\nKeep existing PSA service wrappers blocking until a complete response is\nreceived, despite the communication layer timeout behaviour.\n\nChange-Id: I65d97d32e3bd4cfe326b836336ae637250c70665\nSigned-off-by: Harrison Mutai \u003charrison.mutai@arm.com\u003e\n" }, { "commit": "127f7343d48f1e06b4e5d03da8269f37c21a05f6", "tree": "ff047611bb11e09a6dda729a751102d24c4380bf", "parents": [ "40859e2936c52f0640f6935470cd7e40b74bee6e" ], "author": { "name": "Harrison Mutai", "email": "harrison.mutai@arm.com", "time": "Thu Jun 11 09:01:24 2026" }, "committer": { "name": "Harrison Mutai", "email": "harrison.mutai@arm.com", "time": "Thu Sep 24 13:48:31 2026" }, "message": "feat(psa): support non-blocking attestation calls\n\nAllow delegated attestation/token retrieval operations to return\nimmediately when the operation may outlive the communication timeout.\n\nChange-Id: I5654b55ed09862f2b708bb09b9c365272976d92d\nSigned-off-by: Harrison Mutai \u003charrison.mutai@arm.com\u003e\n" }, { "commit": "40859e2936c52f0640f6935470cd7e40b74bee6e", "tree": "b4fd9d80f580b50b482b53c74772d08d438b9252", "parents": [ "1d8c9630ca53a1d3189fabd0df2be1bc09062e7c" ], "author": { "name": "Harrison Mutai", "email": "harrison.mutai@arm.com", "time": "Thu Jun 11 08:38:01 2026" }, "committer": { "name": "Harrison Mutai", "email": "harrison.mutai@arm.com", "time": "Thu Sep 24 13:48:31 2026" }, "message": "feat(psa): add non-blocking call semantics\n\nIntroduce the return code `PSA_OPERATION_INCOMPLETE`, which may be\nreturned by an implementation such as RSE while waiting for a transport\nresponse.\n\nChange-Id: If3ce6a59e81c82613ed3e5992f6cb8142e51c53a\nSigned-off-by: Harrison Mutai \u003charrison.mutai@arm.com\u003e\n" }, { "commit": "1d8c9630ca53a1d3189fabd0df2be1bc09062e7c", "tree": "c8a1a39a53dfe4c7a080e20846b37f17da832920", "parents": [ "272b42fcf50aefd1f80f34ead9b35fdda0889ec7" ], "author": { "name": "Harrison Mutai", "email": "harrison.mutai@arm.com", "time": "Thu Jun 11 17:32:18 2026" }, "committer": { "name": "Harrison Mutai", "email": "harrison.mutai@arm.com", "time": "Thu Sep 24 13:48:31 2026" }, "message": "feat(firme): enable serialization of attest reqs\n\nAdd begin and finish hooks around platform attestation token requests so\nplatforms can serialize transactions and validate continuation\nownership.\n\nImplement the hooks on RD-V3 to associate an active transaction with its\noriginating FIRME instance. Reject concurrent new requests, deny\ncontinuations from other instances, and reject continuations when no\ntransaction is active.\n\nRetain ownership while an operation is incomplete and release it after\ncompletion or failure.\n\nChange-Id: If62ffb8db723083aa475347c0cbf2f162f7d631d\nSigned-off-by: Harrison Mutai \u003charrison.mutai@arm.com\u003e\n" }, { "commit": "272b42fcf50aefd1f80f34ead9b35fdda0889ec7", "tree": "6a02d63497afb66f722cd93a35a816285555d0ef", "parents": [ "18d7a125b7ed9a52335e10e5583c49f1fe23cf23" ], "author": { "name": "Harrison Mutai", "email": "harrison.mutai@arm.com", "time": "Mon Mar 09 17:39:24 2026" }, "committer": { "name": "Harrison Mutai", "email": "harrison.mutai@arm.com", "time": "Thu Sep 24 12:07:52 2026" }, "message": "feat(fvp): wire in FIRME attestation service\n\nAdd plumbing to support `FIRME_ATT_PAT_GET`.\n\nChange-Id: Ia14ec5144a6be7a4e9b05dbab625a33775cfb747\nSigned-off-by: Harrison Mutai \u003charrison.mutai@arm.com\u003e\n" }, { "commit": "18d7a125b7ed9a52335e10e5583c49f1fe23cf23", "tree": "d80d1a36d19be96a09c81de5eb8880deef5ff9aa", "parents": [ "54ed98453066ecf6d4c9fbf998b2d8a6856c12b9" ], "author": { "name": "Harrison Mutai", "email": "harrison.mutai@arm.com", "time": "Tue Aug 25 13:25:22 2026" }, "committer": { "name": "Harrison Mutai", "email": "harrison.mutai@arm.com", "time": "Thu Sep 24 12:07:52 2026" }, "message": "feat(bl31): relax GPF hardened write alignment rule\n\nThis writer is used to copy things like tokens into the buffers shared\nwith lower-els. Requiring the length of the buffer be 8-byte aligned is\nquite restrictive as there is no such requirement on the length of the\ntoken itself. Handle the tail with a byte-granular path.\n\nChange-Id: If5bebe4cbe8130cba412ac89e953f6203015191e\nSigned-off-by: Harrison Mutai \u003charrison.mutai@arm.com\u003e\n" }, { "commit": "54ed98453066ecf6d4c9fbf998b2d8a6856c12b9", "tree": "4eaa8f036c709a25cc1ca0f9448831c0ab3fe83a", "parents": [ "155522ec4bc373f94677d6599e2fee6ce250c172" ], "author": { "name": "Harrison Mutai", "email": "harrison.mutai@arm.com", "time": "Wed Apr 08 07:48:15 2026" }, "committer": { "name": "Harrison Mutai", "email": "harrison.mutai@arm.com", "time": "Thu Sep 24 12:07:52 2026" }, "message": "feat(firme): introduce FIRME attestation service\n\nAdd attestation service and support for `FIRME_ATTEST_PAT_GET`. This ABI\nis used to enable retrieval of platform attestation tokens.\n\nChange-Id: Iea086eb5cd516d5d8f7dbf78a786b3099fe9b064\nSigned-off-by: Harrison Mutai \u003charrison.mutai@arm.com\u003e\n" }, { "commit": "155522ec4bc373f94677d6599e2fee6ce250c172", "tree": "b45084876846d7a29532b35c1668dd281dc1aaf9", "parents": [ "c09c06e68d1125269045a8c108d3e47529fcdd1f" ], "author": { "name": "Harrison Mutai", "email": "harrison.mutai@arm.com", "time": "Fri Jul 17 14:46:47 2026" }, "committer": { "name": "Harrison Mutai", "email": "harrison.mutai@arm.com", "time": "Thu Sep 24 12:07:52 2026" }, "message": "chore: remove stale error code references\n\nThe alp3 of the FIRME spec reverts RETRY error code to BUSY (ALP0 had\nrenamed BUSY to RETRY). Update our documentation to reflect his change.\n\nChange-Id: I88e8a9a9da9fd840578740072d80881f225bd15d\nSigned-off-by: Harrison Mutai \u003charrison.mutai@arm.com\u003e\n" }, { "commit": "c09c06e68d1125269045a8c108d3e47529fcdd1f", "tree": "285cbcaaef2ccda73ab65c2790eb627cf737c0a1", "parents": [ "8ff67c2f8649eba392e2625425f4fd287608c803", "132b5e2757f7c8a2c7938de498037581bc37e292" ], "author": { "name": "Boyan Karatotev", "email": "boyan.karatotev@arm.com", "time": "Thu Sep 24 12:01:45 2026" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Thu Sep 24 12:01:45 2026" }, "message": "Merge \"fix(build): use absolute path for config header\" into integration" }, { "commit": "8ff67c2f8649eba392e2625425f4fd287608c803", "tree": "cf5e2972e3e6c4e0efeaefee86b65b023dc08628", "parents": [ "259c87420c22a8d690dc24fda456afacbc2111bc", "8bc531c2fc9b51a058d7f424db35ade33eb55c6c" ], "author": { "name": "Chris Kay", "email": "chris.kay@arm.com", "time": "Thu Sep 24 11:15:18 2026" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Thu Sep 24 11:15:18 2026" }, "message": "Merge \"docs(maintainers): add Nix flake code owners\" into integration" }, { "commit": "259c87420c22a8d690dc24fda456afacbc2111bc", "tree": "c02a57594555f69750746bc7d67b683f0d61d1a1", "parents": [ "ccee660cc0b1c79afe8eb52d8e8fef0fe88851fa", "7ea60efa84e14df0816f8c4e5acb9a4040af3046" ], "author": { "name": "Chris Kay", "email": "chris.kay@arm.com", "time": "Thu Sep 24 10:35:40 2026" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Thu Sep 24 10:35:40 2026" }, "message": "Merge \"fix(cpus): re-introduce errata ordering checks\" into integration" }, { "commit": "132b5e2757f7c8a2c7938de498037581bc37e292", "tree": "0f5ada22d29d502d299582528ddb48272afda71d", "parents": [ "cc15123043ed99354c5296f64e5949f2ea05c11f" ], "author": { "name": "Chris Kay", "email": "chris.kay@arm.com", "time": "Thu Sep 24 10:05:23 2026" }, "committer": { "name": "Chris Kay", "email": "chris.kay@arm.com", "time": "Thu Sep 24 10:06:51 2026" }, "message": "fix(build): use absolute path for config header\n\nWe normally construct an absolute path for `BUILD_PLAT`, but callers can\nalso set it on the command line. If they supply a relative path, the\n`-include` option for our generated `config.h` inherits that relative\npath too.\n\nThis works while we\u0027re compiling from the TF-A source directory, but\nMbed TLS is built with CMake, which runs its compiler checks from a\nseparate build directory. The header has already been generated by this\npoint, but the compiler looks for it relative to the wrong directory and\nreports that it doesn\u0027t exist.\n\nResolve the configuration header\u0027s path against the TF-A source\ndirectory so that it remains valid when passed to builds running\nelsewhere, which allows callers to keep using a relative `BUILD_PLAT`\nwithout breaking the Mbed TLS compiler checks.\n\nChange-Id: Id623b050ac12ef9033c4ff57bdc51ce16dbb5361\nSigned-off-by: Chris Kay \u003cchris.kay@arm.com\u003e\n" }, { "commit": "ccee660cc0b1c79afe8eb52d8e8fef0fe88851fa", "tree": "60cc086db07884299caa1224b41d97e9866d984e", "parents": [ "cc15123043ed99354c5296f64e5949f2ea05c11f", "71fa1796b95d7d8012fb2f8c6e2a0ea853a6e60d" ], "author": { "name": "Harrison Mutai", "email": "harrison.mutai@arm.com", "time": "Thu Sep 24 10:00:04 2026" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Thu Sep 24 10:00:04 2026" }, "message": "Merge \"refactor(qti): extract common Hoya macros into hoya_def.h\" into integration" }, { "commit": "cc15123043ed99354c5296f64e5949f2ea05c11f", "tree": "dcec61ee781e6ba0f728033c583c509867361807", "parents": [ "8227f99ddb361db4c4fb8166932f2f83e01b66a7", "85a9fe07868badcad7a411e48ddeda20621ca714" ], "author": { "name": "Boyan Karatotev", "email": "boyan.karatotev@arm.com", "time": "Thu Sep 24 09:38:11 2026" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Thu Sep 24 09:38:11 2026" }, "message": "Merge changes Ib5b075ae,I8967eb71,I622078fa,I6fa2459f,Ie02dc215 into integration\n\n* changes:\n fix(rv1126b): use #if defined for IMAGE_BL flags\n fix(bl1): use #ifdef for some BL1U/BL2U flags\n fix(build): add a default value for XLAT_TABLES_LIB_V2\n fix(build): move DSU flags to Makefile\n fix(el3-runtime): use #if defined for IMAGE_BL flags\n" }, { "commit": "8227f99ddb361db4c4fb8166932f2f83e01b66a7", "tree": "1fdb13666222a66f9ff89ba5151c1ec336ac5bea", "parents": [ "f70bd1c6397d132bc8d41c2d1693256d0eb1594f", "ccb3baefdb03d2eafb8484a47b08053705a3875b" ], "author": { "name": "Chris Kay", "email": "chris.kay@arm.com", "time": "Thu Sep 24 09:23:38 2026" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Thu Sep 24 09:23:38 2026" }, "message": "Merge \"feat(gicv3): explicitly clear IGRPMODR when defaulting interrupts to G1NS\" into integration" }, { "commit": "547f3301f2233e65a0321fa43229a78f1f0a4455", "tree": "044414bb84862632b3e351fef05879eb96b83586", "parents": [ "f70bd1c6397d132bc8d41c2d1693256d0eb1594f" ], "author": { "name": "kennethkabogo", "email": "kennethkabogo2@gmail.com", "time": "Thu Sep 03 05:08:40 2026" }, "committer": { "name": "Kenneth", "email": "kennethkabogo2@gmail.com", "time": "Thu Sep 24 08:58:35 2026" }, "message": "feat(common): make NS range hook a mandatory porting interface\n\nplat_is_valid_ns_address_range() is currently a weak function returning\ntrue unconditionally. A platform that adopts the validation framework\nwithout implementing the hook therefore gets SMC_OK from\nsmc_get_mem_range() for an address in Secure RAM: the overflow check\nstill runs, but the Non-Secure range check silently accepts everything,\nso the framework\u0027s central security property is unenforced while the API\nreports success.\n\nThere is no useful generic answer to \"is this range in Non-Secure\nmemory\" - only the platform knows its own memory map - so remove the\ndefault rather than change what it returns, in line with the project\u0027s\nguidance against weak functions. Platforms that use the framework must\nnow implement the hook, and fail to link if they do not.\n\nDocument the interface in the porting guide, where it was absent\nentirely, including the guarantee that smc_validate_mem_range() rejects\nan overflowing base + size before the hook is called. The one platform\nthat has adopted the framework independently already relies on that\nguarantee without it being written down anywhere.\n\nPlatforms that do not use the framework are unaffected: smc_validation.c\nis in BL31_SOURCES for every platform, but --gc-sections discards\nsmc_validate_mem_range() and its reference to the hook where nothing\ncalls it. Verified by building bl31 for fvp (implements the hook), qemu\n(neither implements nor calls it) and imx8mm (implements it) - all three\nlink.\n\nSuggested-by: Sandrine Afsa \u003csandrine.afsa@arm.com\u003e\nChange-Id: I6810408d89d7ff64bbf8952ed7663249993439c9\nSigned-off-by: kennethkabogo \u003ckennethkabogo2@gmail.com\u003e\n" }, { "commit": "f70bd1c6397d132bc8d41c2d1693256d0eb1594f", "tree": "c97f26c3c9839e7c3ac5d3c472de6691185f53a5", "parents": [ "ca8f225b8450d7d4de0b17302de5b46f02227640", "ea2336bea70955f01aa6d161ebef731916876740" ], "author": { "name": "Boyan Karatotev", "email": "boyan.karatotev@arm.com", "time": "Thu Sep 24 08:58:10 2026" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Thu Sep 24 08:58:10 2026" }, "message": "Merge \"fix(altera): update Agilex3 QSPI Data Base Address\" into integration" }, { "commit": "85a9fe07868badcad7a411e48ddeda20621ca714", "tree": "adcc64b6f6d4cef8e41e7fe943673043f6e59904", "parents": [ "a9f882d2f496bd10aa9eef6df7bd2b28afd092cc" ], "author": { "name": "Yann Gautier", "email": "yann.gautier@st.com", "time": "Wed Sep 23 13:56:39 2026" }, "committer": { "name": "Yann Gautier", "email": "yann.gautier@st.com", "time": "Thu Sep 24 08:44:33 2026" }, "message": "fix(rv1126b): use #if defined for IMAGE_BL flags\n\nThis file was missing in the previous patch[1], and an error is detected\nwhen enabling -Wundef flag.\n\n[1]: b805ef53ebe9 fix(rockchip): use #ifdef for IMAGE_BL flags\n\nChange-Id: Ib5b075ae0b1a285658aef981559f7d69d89c0410\nSigned-off-by: Yann Gautier \u003cyann.gautier@st.com\u003e\n" }, { "commit": "a9f882d2f496bd10aa9eef6df7bd2b28afd092cc", "tree": "6599b9ece48467703806e58c2b5ec0d234471530", "parents": [ "ae7510f1d04014d9f862ccdf4d9f5751d728ac2e" ], "author": { "name": "Yann Gautier", "email": "yann.gautier@st.com", "time": "Wed Sep 23 17:18:55 2026" }, "committer": { "name": "Yann Gautier", "email": "yann.gautier@st.com", "time": "Thu Sep 24 08:44:33 2026" }, "message": "fix(bl1): use #ifdef for some BL1U/BL2U flags\n\nThose flags are defined in C header files, so they are either defined\nor do not exist. This triggers a build error with -Wundef:\n14:38:07 bl1/tbbr/tbbr_img_desc.c:30:5: error: \u0027SCP_BL2U_BASE\u0027 is not\n defined, evaluates to \u00270\u0027 [-Werror\u003dundef]\n14:38:07 30 | #if SCP_BL2U_BASE\n14:38:07 | ^~~~~~~~~~~~~\n14:38:07 bl1/tbbr/tbbr_img_desc.c:41:5: error: \u0027BL2U_BASE\u0027 is not\n defined, evaluates to \u00270\u0027 [-Werror\u003dundef]\n14:38:07 41 | #if BL2U_BASE\n14:38:07 | ^~~~~~~~~\n14:38:07 bl1/tbbr/tbbr_img_desc.c:53:5: error: \u0027NS_BL2U_BASE\u0027 is not\n defined, evaluates to \u00270\u0027 [-Werror\u003dundef]\n14:38:07 53 | #if NS_BL2U_BASE\n14:38:07 | ^~~~~~~~~~~~\n\nOnly the #ifdef should have been sufficient, bu it was changing the\nbehavior, as a value defined to 0 would have added the entry to the\ntable. So we check both the existence of a flag and that is is non null.\n\nChange-Id: I8967eb71e438c56b2d4c1789a1b89d2f488b37ab\nSigned-off-by: Yann Gautier \u003cyann.gautier@st.com\u003e\n" }, { "commit": "ae7510f1d04014d9f862ccdf4d9f5751d728ac2e", "tree": "3ae78e012cd4fd13f854732c53e10ec4016c193b", "parents": [ "29e3ae744b1c8bd3da8e0d481c9c59cb661ac80a" ], "author": { "name": "Yann Gautier", "email": "yann.gautier@st.com", "time": "Wed Sep 23 16:38:02 2026" }, "committer": { "name": "Yann Gautier", "email": "yann.gautier@st.com", "time": "Thu Sep 24 08:44:33 2026" }, "message": "fix(build): add a default value for XLAT_TABLES_LIB_V2\n\nFor platforms that do not use the version 2 of translation tables lib,\nthere is a build error when enabling -Wundef. To avoid this, always\ndefine XLAT_TABLES_LIB_V2. By default, it is 0, and for platforms that\nalready include lib/xlat_tables_v2/xlat_tables.mk, it will be defined\nto 0. And move the C flags definition to Makefile.\n\nChange-Id: I622078fa6da7dd5bff78abc342e6cf1350bc3cd5\nSigned-off-by: Yann Gautier \u003cyann.gautier@st.com\u003e\n" }, { "commit": "29e3ae744b1c8bd3da8e0d481c9c59cb661ac80a", "tree": "534373e23894014304e590ad5e047a1ffc382ba7", "parents": [ "139cd13b06a4e01e7b4c88ae434bfe813784ac20" ], "author": { "name": "Yann Gautier", "email": "yann.gautier@st.com", "time": "Wed Sep 23 14:31:50 2026" }, "committer": { "name": "Yann Gautier", "email": "yann.gautier@st.com", "time": "Thu Sep 24 08:44:30 2026" }, "message": "fix(build): move DSU flags to Makefile\n\nThe flags DSU_PDL2_SUPPORT \u0026 USE_DSU_DRIVER are already handled in the\nmake_helpers/defaults.mk file, and defined as 0. Defining them only in\nbl31.mk leads to compilation errors when building with -Wundef:\ninclude/plat/arm/common/arm_def.h:51:5: error: \u0027DSU_PDL2_SUPPORT\u0027 is not\n defined, evaluates to \u00270\u0027 [-Werror\u003dundef]\n 51 | #if DSU_PDL2_SUPPORT\n | ^~~~~~~~~~~~~~~~\n\nMove their definition to Makefile.\n\nChange-Id: I6fa2459fcd987cf8940388abfc0edd8ae6f2297a\nSigned-off-by: Yann Gautier \u003cyann.gautier@st.com\u003e\n" }, { "commit": "139cd13b06a4e01e7b4c88ae434bfe813784ac20", "tree": "92577678faf03c557f8f89dea13dd6f565dab1dd", "parents": [ "ca8f225b8450d7d4de0b17302de5b46f02227640" ], "author": { "name": "Yann Gautier", "email": "yann.gautier@st.com", "time": "Wed Sep 23 13:54:22 2026" }, "committer": { "name": "Yann Gautier", "email": "yann.gautier@st.com", "time": "Thu Sep 24 08:43:45 2026" }, "message": "fix(el3-runtime): use #if defined for IMAGE_BL flags\n\nThis one was missing in the previous patch[1], and an error is detected\nwhen enabling -Wundef flag.\n\n[1]: 463b9be45f76 (\"fix(el3-runtime): use #ifdef for IMAGE_BL flags\")\n\nChange-Id: Ie02dc2154f5ce429968e5ceec3eadd1744299111\nSigned-off-by: Yann Gautier \u003cyann.gautier@st.com\u003e\n" } ], "next": "ea2336bea70955f01aa6d161ebef731916876740" }